A typical image sensor senses light by converting photons into electrons or holes that are integrated (collected) in sensor pixels, when the sensor is exposed to light. After completion of an integration cycle, the collected charges are converted into a voltage, which can then be output at the output terminals of the sensor. In CMOS image sensors, the charge-to-voltage conversion is accomplished directly at a pixel device, and the resulting analog pixel voltage is then transferred to the output terminals through various pixel addressing and scanning schemes. The analog signal can be also converted on-chip to a digital equivalent signal before reaching the chip output. Typically, a pixel device is also coupled with a buffer amplifier (e.g., a Source Follower (SF)), which drives the sense lines with the digital equivalent signal that are connected to the pixels by suitable addressing transistors. After the charge-to-voltage conversion is completed, and the resulting signal is transferred out from the pixels, the pixels can be reset for accumulation of new charges in a new exposure.
In pixels that use Floating Diffusion (FD) as a charge detection node, the reset is accomplished by turning on a reset transistor that charges the FD node to a reference voltage. While the resetting removes the collected charges, it also generates kTC-reset noise. The kTC-reset noise can be removed by Correlated Double Sampling (CDS) signal processing technique in order to achieve the desired low noise performance.
The typical CMOS image sensors that utilize the CDS concept usually require three transistors (3T) or four transistors (4T) in the pixel, one of which serves as the charge transferring (TX) transistor. It is possible to share the drain or source terminals of the pixel circuit transistors among several photodiodes to reduce the pixel size. To avoid light from being blocked by the metal interconnects and electrodes of the devices coupled to the pixel (e.g., the reset transistor, the charge transferring transistor, etc.), a back-illuminated CMOS image sensor pixel structure can be used, where light is incident on a side of the substrate that is different from the side where the metal interconnects and electrodes are located.
Besides kTC-reset noise, another noise source of an image sensor device is dark current. Dark current refers to an electric current that flows through the sensor device when no photons enter the device. One source of dark current is due to interface trapping. A solid-state image sensor device is typically fabricated on a silicon substrate. The device typically includes insulator layers (e.g., silicon dioxide). There are typically electrically active defects located at the interface between the insulator and the silicon. Those defects can trap charges. The trapping of the charges can lead to a generation of charge carriers not converted from photons. Since the dark current can add charge carriers that are not generated by incident light photons, the dark current does not correlate with the sensed light, and the accuracy of the image sensor will be degraded as a result.
An example of a back-illuminated CMOS image sensor pixel structure 100 under the current technology is shown in FIG. 1. For the rest of disclosure, “n region” or “n layer” refers to a region that includes n-type dopants, while “p region” or “p layer” refers to a region that includes p-type dopants. Moreover, an “n+ region” refers to a region that has a higher concentration of n-type dopants than an “n region”, which has a higher concentration of n-type dopants than an “n− region.” Moreover, a “p+ region” refers to a region that has a higher concentration of p-type dopants than a “p region”, which has a higher concentration of p-type dopants than a “p− region.”
As shown in FIG. 1, CMOS image sensor pixel structure 100 includes a plurality of pixel regions including, for example, a p+ floating diffusion region 104, a p region 105, and a first charge transfer gate 110. CMOS image sensor pixel structure 100 also includes a second charge transfer gate 112 and a p+ region 113. Both p+ floating diffusion region 104 and p+ region 113 are in an n-well 109 and, together with second charge transfer gate 112, can form a PMOS device.
As to be discussed below, photons can enter CMOS image sensor pixel structure 100 when the pixel structure 100 is exposed to light, which can lead to formation of positive charges in p region 105. A FD1 terminal can be connected to p+ floating diffusion region 104 on a front side of CMOS image sensor pixel structure 100, and a TX1 terminal can be connected to first charge transfer gate 110 on the front side. During the integration cycle, a voltage can be applied to TX1 terminal to enable a transfer of the charges formed in p region 105 to p+ floating diffusion region 104. Charges stored at the parasitic capacitors of p+ floating diffusion region 104 can develop a voltage. Terminal FD1 can be connected to a buffer amplifier (e.g., a Source Follower (SF)), which can be configured to sense the voltage developed at p+ floating diffusion region 104, and to drive the sense lines with a digital signal equivalent to the sensed voltage.
Moreover, a GND1 terminal can be connected to p+ region 113 on the front side, and a RST1 terminal can be connected to second charge transfer gate 112 on the front side. GND1 terminal can be connected to a fixed bias voltage with a value of, for example, zero volts. At the end of the integration cycle, a voltage can be applied to RST1 terminal to enable a transfer of the charges in p+ floating diffusion region 104 to p+ region 113, to reset p+ floating diffusion region 104 for accumulation of new charges in the next integration cycle.
As shown in FIG. 1, CMOS image sensor pixel structure 100 further includes a silicon substrate 106 that includes an n+ layer 102 implanted in a back side that is opposite to the front side, with the dopants of the n+ layer 102 activated by, for example, laser annealing. The front side of silicon substrate 106 is covered by an oxide layer 107 configured to isolate first charge transfer gate 110 from the sensor layer 106. A front side interface 101a is formed between oxide layer 107 and silicon substrate 106. Silicon substrate 106 further includes a p− region 103 situated above the n+ layer 102. Silicon substrate 106 further includes an n+ potential pinning layer 108 above p region 105. A photodiode (PD) can be formed between, for example, a p region including p− region 103 and a p region 105, and an n region including n+ potential pinning layer 108.
CMOS image sensor pixel structure 100 further includes, on the back side, an insulating layer 114, an anti-reflecting layer 115, color filter elements 116, and a micro lens 117. Anti-reflecting layer 115, color filter elements 116, and micro lens 117 are configured to control one or more attributes of light that enters silicon substrate 106. For example, micro lens 117 can focus the incident light. Color filter elements 116 can control which color components of the light can enter silicon substrate 106. Anti-reflecting layer 115 prevents the reflection of light, to reduce the incident light loss. Insulating layer 114 further insulates silicon substrate 106 from the external environment around the back surface. A back side interface 101b is formed between insulating layer 114 and n+ layer 102.
Photons can enter CMOS image sensor pixel structure 100 from the back surface of the sensor layer 106 through micro lens 117, color filter elements 116, anti-reflecting layer 115 and insulating layer 114. The photons can generate carriers in the p− region 103, and the charges of these carriers are collected in the potential well of the photodiode (PD) formed in p region 105. The charges can then be transferred, via charge transfer gate 110, to the floating diffusion region 104.
The n+ layer 102 can provide negative charges that can combine with the traps at back side interface 101b, thereby preventing the p-type carriers in p− region 103, activated by the photons, from combining with the traps. As a result, the number of the generated carriers at p− region 103 can reflect more accurately the amount of photons received. Further, the n+ potential pinning layer 108 can also provide negative carriers to combine with the traps at front side interface 101a between oxide layer 107 and silicon substrate 106, to further reduce the dark current generated at that interface.
Further, the p+ floating diffusion region 104 is included in the n-well 109. With n-well 109 typically connected to a positive potential, n-well 109 can divert the photon generated positive charges into the photodiode potential well located in p region 105, to prevent or mitigate charge loss. The CMOS image sensor pixel structure 100 further includes an n region 111a that extends between potential pinning layer n+ layer 108 and n+ layer 102, to isolate the p regions (e.g., p region 105, p− region 103, etc.) of CMOS image sensor pixel structure 100 from the p regions of a neighboring pixel structure. Moreover, the CMOS image sensor pixel structure 100 also includes an n region 111b that extends between n-well 109 and the n+ layer 102, also to isolate p− region 103 from the p regions of a neighboring pixel structure.
As discussed before, one source of dark current is due to interface trapping. Such traps can be formed at, for example, back side interface 101a, as well as front side interface 101b. The generation of excessive dark current can be mitigated by reducing the interface states in back side interface 101, to improve the accuracy of CMOS image sensor pixel structure 100. As illustrated in FIG. 1, this can be accomplished by introducing the n+ layer 102 and the n+ potential pinning layer 108 to reduce the interface states generated dark current.
The n+ layer 102 can be formed using ion implantation, by imparting ions from the front side of silicon substrate 106 for them to reach the back side. However, it is difficult to form an n+ layer at the back side with high doping concentration using ion implantation. Moreover, a thick layer of n+ layer 102 is typically required to achieve the requisite doping concentration. However, a thick n+ layer 102 can degrade the sensitivity. This is because the positive carriers generated by photons entering from the back side surface can recombine with the negative carriers within n+ layer 102, instead of being collected in the potential well of the photodiode (PD) formed in region 105. Therefore, fewer positive carriers are generated for a certain amount of photons (which corresponds to a certain intensity of incident light), and the sensitivity of CMOS image sensor pixel structure 100 can be degraded as a result.
On the other hand, n+ layer 102 can also be formed by back side implant and thermal activation processes. However, both processes are complex and expensive.